1. Field of the Invention
The present invention relates to a memory module which is made up of a volatile memory such as DRAM, SRAM or the like as well as a re-writable non-volatile memory such as E2PROM or the like.
2. Description of the Related Art
In recent information processing apparatuses such as personal computers, workstation server computers and the like, a main storage device has an increasingly larger storage capacity in line with a faster processing speed provided by a CPU and an increased number of bits processed thereby, resulting in employment of memory modules such as SIMM (Single Inline Memory Module), DIMM (Dual Inline Memory Module), MCP (Multi Chip Package) and the like.
FIG. 1 is a plan view illustrating an exemplary configuration of a memory module, and FIG. 2 is a side view illustrating an exemplary configuration of another memory module.
As illustrated in FIGS. 1 and 2, each of the memory modules comprises a plurality of volatile memories 1 such as DRAM, and re-writable non-volatile memory 2 such as E2PROM, both of which are mounted on the same substrate 3. Specifically, FIG. 1 illustrates an exemplary configuration of SIMM (or DIMM), while FIG. 2 illustrates an exemplary configuration of MCP which has non-volatile memory 2 stacked on volatile memory 1.
These memory modules have a plurality of volatile memories 1 which are commonly applied with address signals A0-An (n is a positive integer) for writing/reading data; control signals RAS (Row address strobe command), CAS (Column address strobe command), WE (Write enable) for setting volatile memories 1 in a predetermined operation mode; and control signal CS (chip select) for selecting a memory to be activated. Each volatile memory 1 receives or delivers a DQ signal which is input/output data, and a DQM signal for masking the DQ signal in accordance with bits assigned to respective volatile memories 1.
A bank refers to a parallelly accessible memory area in a memory module which is selected by control signal CS. For example, in DIMM, volatile memories 1 mounted on one side of a substrate are set to bank 0, while non-volatile memories 1 mounted on the other side are set to bank 1.
On the other hand, non-volatile memory 2 previously stores information such as the configuration, type, characteristics and the like of the associated memory module, which is used by a system (information processing apparatus or the like) that is equipped with the memory module.
Next, the configuration of volatile memories 1 illustrated in FIGS. 1 and 2 will be described with reference to FIGS. 3 to 7. The volatile memory illustrated in FIG. 3 shows an exemplary configuration of conventional SDRAM (Synchronous DRAM).
AS illustrated in FIG. 3, conventional volatile memory 1 comprises memory cell array (MC ARRAY) 11 composed of a plurality of memory cells MC for storing data; a plurality of sense amplifiers 12 each for reading data stored in associated memory cell MC; row decoder (X DEC) 13 and column decoder (Y DEC) 14 for decoding address signal ADD for accessing memory cell into which data is written or from which data is read; a plurality of column switches (Y SW) 15 each for turning on/off the output of associated sense amplifier 12 in accordance with the result of decoding by column decoder 14; data latch circuit (D LAT) 16 for temporarily holding data which is to be written into memory cell MC; output latch circuit (O LAT) 17 for temporarily holding data read from memory cell MC; row address latch circuit (X ADD LAT) 18 for temporarily holding a row address supplied to row decoder 13; column address latch circuit (Y ADD LAT) 19 for temporarily holding a column address supplied to column decoder 14; command decoder (CMD DEC) 20 for decoding a control command supplied from the outside for setting volatile memory 1 in any of various operation mode; initial setting register (INT REG) 21 for holding mode setting information such as a CAS latency, a burst length and a burst type; control circuit (CONT) 22 for controlling a data write operation to memory cell array 11 and a data read operation from memory cell array 11 in response to an output signal of command decoder 20; data input buffer circuit 23 for receiving data supplied from the outside to pass the received data to data latch circuit 16; and data output buffer circuit 24 for delivering data fed from output latch circuit 17 to the outside.
In addition to normal memory cell area (NMC) 111 which is a memory cell area for normal use, memory cell array 11 also comprises redundant row memory cell area (X RNC) 112 and redundant column memory cell area (Y RNC) 113 which are formed with redundant memory cells for replacement in the event of a fault in any memory cell within normal memory cell area 111.
Row decoder 13 comprises normal row decoder (X NDEC) 131 and redundant row decoder (X RDEC) 132 associated with normal memory cell area 111 and redundant row memory cell area 112, respectively. Column decoder 14 in turn comprises normal column decoder (Y NDEC) 141 and redundant column decoder (Y RDEC) 142 associated with normal memory cell area 111 and redundant column memory cell area 113, respectively. Column switch 15 further comprises normal column switch (Y NSW) 151 and redundant column switch (Y RSW) 152 associated with normal memory cell area 111 and redundant column memory cell area 113, respectively.
As illustrated in FIG. 4, initial setting register 21 comprises n address latch circuits 2101-210n for holding address signals A0-An on a bit-by-bit basis; and a plurality of mode latch circuits 211 for holding control signals /RAS, /CAS, /WE, /CS, respectively. In synchronization with clock CLK applied from the outside, initial setting register 21 delivers latch signals IA0-IAn, IA0B-IAnB, control signals /RAS, /CAS, /WE, /CAS and their inverted versions. It should be noted that though FIG. 4 shows only one mode latch circuit 211, mode latch circuits 211 are provided corresponding to control signals /RAS, /CAS, /WE, /CS, respectively.
Command decoder 20 comprises latency setting decoder 201, burst length setting decoder 202 and burst type setting decoder 203 for decoding latch signals IA0-IAm, IA0B-IAmB (m is a positive integer smaller than n: m less than n) out of latch signals IA0-IAn, IA0B-IAnB delivered from address latch circuits 2101-210n for use as the mode setting information, to deliver mode setting results which include the CAS latency, burst length and burst type; mode register setting decoder 204 for decoding control signals /RAS, /CAS, /WE, /CS delivered from mode latch circuit 211 to deliver mode register activation signal MRS; delay circuit 205 for delaying clock signal CLK applied from the outside by a predetermined time; logical AND gate 206 for delivering logical AND of mode register activation signal MRS and the clock signal delivered from delay circuit 205; and mode latch circuit 2071-2073 for holding output signals of latency setting decoder 201, burst length setting decoder 202 and burst type setting decoder 203 in synchronization with a timing clock delivered from logical AND gate 206.
Initial setting register 21 and command decoder 20 illustrated in FIG. 4 function as mode registers, each of which holds data such as the CAS latency, burst length and burst type that are set using address signals A0-Am. Latency setting decoder 201, burst length setting decoder 202, and burst type setting decoder 203 deliver their respective decoding results when address signal Am+1 is xe2x80x9c0xe2x80x9d. A latency signal, a burst length signal and a burst type signal delivered from mode latch circuits 2071-2073, respectively, are held unchanged until next mode register activation signal MRS is delivered, or until the next mode setting is made.
As illustrated in FIG. 5, upon setting of the mode registers, control signals /RAS, /CAS, /WE, /CS, and latch signals IA0-IAm+1, IA0B-IAm+1B are fetched into volatile memory 1 in synchronization with a rising edge of clock CLK (held in address latch circuits 2101-210n), and written into the mode registers in synchronization with a rising edge of the timing clock applied to mode latch circuits 2071-2073.
Address signals A0-Am are used for setting the CAS latency, burst length and burst type, while address signal Am+1 is set to xe2x80x9c0xe2x80x9d when the mode registers are set.
As illustrated in FIG. 6, redundant row decoder 132 comprises redundant row decoder transistors 1330-1332m which have their drains and sources connected in common and are turned on/off under control of internal row address signals ALX0-ALXm, ALX0B-ALXmB delivered from row address latch circuit 18; precharge transistor 134 which is turned on/off under control of precharge signal Pxrd delivered from control circuit 22 for supplying power supply voltage VDD to the drains of respective redundant row decoder transistors 1330-1332m; and logical AND gate 135 for delivering logical AND of an output signal of precharge transistor 134 and selection signal RWE delivered from control circuit 22 for selecting a redundant word line.
Redundant row decoder transistors 1330-1332m have their sources connected to a ground, and are provided with fuse element 1360-1362m, which can be cut by laser light, between their drains and node N1, respectively.
Fuse elements 1360-1362m are blown out by laser light based on a row address of a memory cell which is determined as defective in a test after wafer manufacturing. For example, when a fault occurs in a memory cell which has the least significant bit set at xe2x80x9c1xe2x80x9d and the remaining bits set at xe2x80x9c0xe2x80x9d, all fuse elements 136, which are cut in this event, are provided at the drains of those redundant row decoder transistors 133 which are applied with internal row address signals ALX0, ALX0B-ALXmB. In another example, when a fault occurs in a memory cell which has the least significant bit set at xe2x80x9c0xe2x80x9d and the remaining bits set at xe2x80x9c1xe2x80x9d, all fuse elements 136 which are cut in this event, are provided at the drains of those redundant row decoder transistors 133 which are applied with internal row address signals ALX0B, ALX0-ALXm.
With the use of plurality of such fuse elements which can be blown out by laser light for holding information for accessing a redundant memory cell through laser trimming, application of row address signals A0-Am corresponding to a memory cell determined as defective causes connection node N between redundant row decoder transistor 133 and precharge transistor 134 to go to xe2x80x9cHighxe2x80x9d (VDD), resulting in activation of output signal RWL1 from logical AND gate 135. Since the output line of logical AND gate 135 serves as a word line in redundant row memory cell area 112, the application of the address of a memory cell determined as defective results in an access to a memory connected to activated word line RWL1 in redundant row memory cell area 112 instead of that memory cell.
Redundant row decoder 132 comprises a plurality of sets of redundant row decoder transistors 1330-1332m, precharge transistor 134 and logical AND gate 135, illustrated in FIG. 6, such that when a plurality of defective memory cells are detected, the laser trimming is performed for each of sets corresponding to the addresses of the respective defective memory cells.
As illustrated in FIG. 7, conventional redundant column decoder 142 is similar in configuration to redundant row decoder 132 illustrated in FIG. 6, and comprises redundant column decoder transistors 1430-1432m which have their drains and sources connected in common and are turned on/off under control of internal column address signals ALY0-ALYm, ALY0B-ALYmB delivered from column address latch circuit 19; precharge transistor 144 which is turned on/off under control of precharge signal Pyrd delivered from control circuit 22 for supplying power supply voltage VDD to the drains of respective redundant column decoder transistors 1430-1432m; and logical AND gate 145 for delivering logical AND of an output signal of precharge transistor 144 and selection signal RYE delivered from control circuit 22 for selecting a redundant word line. Redundant column decoder transistors 1430-1432m have their source connected to the ground, and are provided with fuse elements 1460-1462m, which can be cut by laser light, between their drains and node N2, respectively.
Fuse elements 1460-1462m are blown out by laser light based on a column address of a memory cell which is determined as defective in a test after wafer manufacturing, in a manner similar to redundant row decoder 132.
The remaining memory cell array 11, sense amplifiers 12, normal row decoder circuit 131, normal column decoder circuit 141, column switch 15, data latch circuit 16, output latch circuit 17, row address latch circuit 18, column address latch circuit 19, control circuit 22, data input buffer circuit 23, and data output buffer circuit 24 are not directly related to the present invention in configuration, so that detailed description thereon is omitted. These circuits may be implemented by any known configurations as long as they satisfy predetermined functions. Also, non-volatile memory 2 may be in any known configuration as long as it is re-writable, for example, E2PROM.
Next, a conventional procedure of manufacturing the memory module in the foregoing configuration will be described with reference to FIGS. 8 and 9.
FIG. 8 is a flow chart illustrating a general procedure of manufacturing a memory module, and FIG. 9 is a flow chart illustrating a processing procedure for conducting an electric test on a conventional memory module.
As illustrated in FIG. 8, first, in a memory module manufacturing process, memory cell array is tested at the time a wafer for volatile memories 1 has been manufactured to identify defective memory cells, at step S1.
Next, a defect recovery is performed for substituting a redundant memory cell for a defective memory cell through the aforementioned laser trimming, at step S2, followed by a test which is conducted again on the wafer to determine whether memory cell array 11 passes or fails, at step S3.
Subsequently, a wafer determined as good in the test is accommodated in a mold package for assembling volatile memory 1, at step S4.
Next, a first electric test is conducted on assembled volatile memory 1 to confirm the performance of individual volatile memory 1, at step S5.
Next, after a burn-in test is conducted in a predetermined condition, at step S6, a second electric test is conducted on volatile memory 1 to confirm the performance after the burn-in test, at step S7. If no defect is found in the second electric test, individual volatile memory 1 is completed, at step S8.
Next, completed individual volatile memory 1, and non-volatile memory 2 manufactured in a similar process are introduced into a memory module manufacturing process, at step S9, wherein volatile memory 1 and non-volatile memory 2 are each mounted on substrate 3 of the memory module, at step S10.
Subsequently, volatile memory 1 and non-volatile memory 2 are each fixed on substrate 3 of the memory module, followed by a solder reflow step which connects a circuit pattern formed on substrate 2 to external terminals of volatile memory 1 and non-volatile memory 2 by soldering, at step S11.
Finally, an electric test is conducted on the memory module, at step S12, and the memory module is completed when no defect is detected, at step S13.
As illustrated in FIG. 9, the electric test for a memory module involves initially writing predetermined data into a non-volatile memory (E2PROM) mounted on the substrate of the memory module, and reading the written data to verify the contents, at step S21.
Next, a plurality of volatile memories mounted on the same substrate are tested in a similar procedure to that for the non-volatile memory, at step S22.
Then, it is confirmed from the result of the test whether or not any defect is found, at step S23, and the memory module is completed if no defect is found. Conversely, if any defect is found, a defective volatile memory is replaced with a new volatile memory, at step S24, followed by the procedure returning to step 22, where the electric test is again conducted on the volatile memory mounted on the memory module.
As described above, in the conventional memory module manufacturing process, a test is conducted at the end of wafer manufacturing to identify defective memory cells which are replaced with redundant memory cells previously formed on the same wafer to recover the defective memory.
However, in recent volatile memories, non-volatile memories and the like, increasing miniaturization of memory cells causes an increasingly lower yield rate. In addition, a larger proportion of memory cells are made defective due to stresses applied thereto during the burn-in test which is conducted after the assembly of the memory. Furthermore, as an increased number of volatile memories and non-volatile memories are mounted on the same substrate of a memory module, a lower yield rate is also presented by the memory modules. Though determined as good in the electric test on individual memories, not a few products are made defective due to a thermal stress applied thereto in the solder reflow step for the assembly into a module.
Basically, there is no other choice but to discard those semiconductor memories determined as defective in the electric test on individual memories or the electric test on memory modules. Particularly, when determined as defective in the electric test on memory modules, since defective memories are manually replaced with new memories, a long working time required therefor constitutes a factor of increasing the cost of the memory module.
It is therefore an object of the present invention to provide a method of recovering a memory module, which is capable of recovering a defective memory cell without replacement, even if it is determined so in an electric test conducted thereon, and to provide a memory module.
To achieve the above object, the present invention involves previously storing a defective row address and a defective column address corresponding to a memory cell in a volatile memory determined as defective, and defective device information for discriminating the volatile memory determined as defective in a non-volatile memory, transferring the defective row address, defective column address and defective device information stored in the non-volatile memory to a volatile memory upon start-up of a system equipped with the memory module for holding the transferred defective row address, defective column address and defective device information in the volatile memory, and accessing a redundant memory cell instead of the memory cell in the volatile memory determined as defective when a fed address corresponds to the defective memory cell, based on the defective row address, defective column address and defective device information held in the volatile memory.
Thus, even if a defect is found in a memory cell of the volatile memory in an electric test on the memory module, the defective memory cell can be recovered, thereby improving the yield rate for the memory module. In addition, since neither replacement nor discard is needed for a volatile memory in which a defect is found, it is possible to prevent an increased cost of the memory module due to an increased working time which would otherwise be required for replacement or discard.
The above and other objects, features, and advantages of the present invention will become apparent from the following description based on the accompanying drawings which illustrate examples of preferred embodiments of the present invention.